This invention relates to divider circuitry and, in particular, to fractional frequency divider circuitry.
A known prior art scheme for dividing an input clock signal (f1) by a fractional number (e.g., 8.25) includes the application of the clock signal (f1) to a controllable integer divider network. By way of example, if it is desired to divide f1 by 8.25, the controllable divider may be programmed to divide by 8 for three sets of 8 complete clock cycles of f1 and to divide by 9 for one set of 9 complete clock cycles of f1. The result is that the output clock signal (fo) of the controllable divider network will contain four full cycles for every 33 complete clock cycles of the input clock signal f1.
A problem with this prior art scheme is that there is a significant lack of symmetry in the waveshape of the output clock signal (fo) when the 3 output clock cycles produced from the divide by 8 cycles are compared to the clock cycle produced from the divide by 9 cycle. That is, for every 4 cycles of the output clock, 3 cycles will each have a period of 8/f1 and one cycle will have a period of 9/f1. In many applications such as in frequency synthesizers and in clock recovery circuits where reliance is placed on phase detection, the asymmetry in the period of the cycles of the output clock (fo) results in the generation of phase errors, even though the output clock has the desired frequency. This is undesirable since phase errors result in the generation and presence of jitter (which is equivalent to noise) in the signals propagated and processed in the system.